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Principal Digital IP Design Engineer (f/m/d)
NXP Semiconductors —München
Generate comprehensive design documentation and participate in design reviews. Ensure IP design implementation is done according to design for testability (DFT)…
16 Std.
Principal Digital IP Verification Engineer (f/m/d)
NXP Semiconductors —München
This position is intended to strengthen the Munich team with experienced verification engineers working across multiple digital IP and subsystem domains.
16 Std.

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Principal Digital IP Verification Engineer (f/m/d)

NXP Semiconductors -
München

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Details zur Stelle

Vollzeit
vor 16 Stunden

Qualifikationen

Informatik
FPGA
Master
Verilog
C++
C
Bachelor
Perl
Scripting
Elektrotechnik
Kommunikationsfähigkeit
Python
Debugging

Vollständige Stellenbeschreibung

Business Line Description

The MCU/MPU Engineering Digital IP team defines and develops components for a wide range of products, including automotive microprocessors, application processors, microcontrollers, and networking solutions.The Munich Digital IP team focuses on the development of interface components, DSP subsystems, next-generation AI/ML cores, and RISC-V-based IP. This position is intended to strengthen the Munich team with experienced verification engineers working across multiple digital IP and subsystem domains.

Key Responsibilities

Perform pre-silicon verification of AI/ML processing blocks, RISC-V processors, or similar digital IPs.
Define and develop comprehensive IP verification plans based on requirements such as industry standards, product requirements, architecture, and design specifications.
Collaborate closely with hardware, firmware, and software teams, as well as architecture and system engineering teams, to understand IP functionality and system-level use cases.
Execute verification plans in alignment with product specifications to ensure high-quality, zero-defect IP delivery.
Architect, develop, debug, and maintain UVM-based verification environments for RTL simulation.
Develop testcases within appropriate verification frameworks, including stimulus generation and assertion-based verification.
Run simulations across multiple abstraction levels (RTL, power-aware RTL, gate-level, FPGA, and emulation platforms).
Execute regressions, analyze results, and drive closure of functional and code coverage.
Identify issues, debug failures, and contribute to continuous improvement of verification methodologies and flows.

Qualifications

Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.
Minimum 10 years of experience in IP or subsystem verification.
Solid understanding of microprocessor architecture, interconnects, and cache coherency mechanisms.
Hands-on experience with CPU verification (proprietary cores, RISC-V, or AI/ML accelerators).
Experience in using AI-based tools to enhance development and verification efficiency.
Strong experience in testbench development using UVM for IP, subsystems, or SoC-level verification.
Experience with AMBA protocols (AHB, AXI, ACE, CHI) and memory systems (ROM, RAM, Flash, DDR/LPDDR).
Advanced knowledge of Verilog, SystemVerilog, and C/C++.
Proficiency in scripting languages such as Python, Perl, TCL, or Shell.
Strong understanding of metric-driven verification, including functional and code coverage.
Experience with directed and constrained-random verification methodologies.
Working knowledge of formal verification techniques and assertion-based verification.
Experience debugging designs in both pre-silicon (simulation/emulation) and post-silicon environments.
Strong analytical and problem-solving skills.
Excellent written and verbal communication skills in English.
Basic conversational German is a plus.

Please note: The successful candidate may/will be responsible for security related tasks. The assignment may/will be in scope of security certifications, therefore a conscious and reliable way of working is necessary .

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