20 beste Stellen als platform engineer in stuttgart, bw – aktuell auf Personalsuche

Senior Formal Verification Engineer
TechBiz Global GmbH —Stuttgart
- Vollzeit
- Homeoffice
- Doktorat
- Master
- Bachelor
Direkt bewerben
10 Tage
Staff Software Engineer - Linux Build Systems & Toolchain
TeamViewer Germany GmbH —Stuttgart
- Hybrides Arbeiten
- Informatik
- C++
- Linux
Direkt bewerben
Trainee Cloud & Data - Dein Einstieg in Artificial Intelligence & Data (m/w/d)
Deloitte Consulting GmbH —Stuttgart
- Online-Bewerbung
- Azure
- Englisch
- Java
- Weiterbildungsprogramme
- Aufstiegsmöglichkeiten
Senior Backend / Infrastructure Engineer (m/w/d) für das INSPO Team // Remote möglich
E. Breuninger GmbH & Co. —Stuttgart
- Vollzeit
- Englisch
- Java
- AWS
- Homeoffice-Möglichkeit
Direkt bewerben
Staff Software Engineer - Fullstack
TeamViewer Germany GmbH —Stuttgart
- Hybrides Arbeiten
- Azure
- SQL
- C++
Direkt bewerben
Senior/Staff Software Engineer Java
TeamViewer Germany GmbH —Stuttgart
- Hybrides Arbeiten
- Azure
- Java
- AWS
Direkt bewerben
R&D Engineer (m/f/d) Software Development (Java)
Advantest —Böblingen
- Informatik
- Java
- Scripting
Integration Engineer - Enterprise Integrations (f/m/x)
SPARETECH —Stuttgart
- Homeoffice
- ERP-Systeme
- Java
- APIs
- Homeoffice-Möglichkeit
- Mitgliedschaft im Fitnessstudio
6 Tage
Data Scientist
Agile Defense —Stuttgart
- Azure
- SQL
- AWS
Direkt bewerben
BOC Specialist 4 - Stuttgart, Germany
M.C. Dean, Inc —Stuttgart
- Vollzeit
- AutoCAD
- Microsoft Office
- Hochschulreife
Software Engineer C#/C++ - AWG with Focus on Hardware and Measurement Science
Keysight Technologies, Inc. —Böblingen
- Vollzeit
- Informatik
- Master
- C++
7 Tage
Product & Platform Engineering Expert (all genders)
Accenture —Stuttgart
- Vollzeit
- Englisch
- Projektmanagement
- Künstliche Intelligenz
EUCOM Cyber Operations Systems Engineer
The MITRE Corporation —Stuttgart
- Vollzeit
- Doktorat
- Master
- Bachelor
3 Std.
Principal Security Engineer
Vay —Stuttgart
- Softwareentwicklung
Direkt bewerben
PREEvision Engineer (m/w/d)
Versigent —Böblingen
- Java
- Präsentationserfahrung
- Elektrotechnik
R&D Engineer, Hardware - High Speed Digital Board Design
Keysight Technologies, Inc. —Böblingen
- Vollzeit
- Englisch
- Master
- Bachelor
7 Tage
Principal Data Engineer (m/f/d)
Thoughtworks —Stuttgart
- Vertrieb
- Systemdesign
Direkt bewerben
AI DevOps Engineer (all genders)
AEB SE —Stuttgart
- Vollzeit
- Azure
- Künstliche Intelligenz
- Flexible Arbeitszeiten
Direkt bewerben
Work Student, Quality Assurance
TeamViewer Germany GmbH —Stuttgart
- 1.253 € – 1.566 € pro Monat
- Vollzeit
- Windows
- Java
- Master
Direkt bewerben
5 Tage
Data Platform Architect (w/m/d)
GFT Technologies SE —Stuttgart
- Azure
- Englisch
- AWS
- Homeoffice-Möglichkeit
- Weiterbildungsprogramme

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Senior Formal Verification Engineer

TechBiz Global GmbH
Stuttgart

Direkt bewerben

Details zur Stelle

Vollzeit
vor 10 Tagen

Qualifikationen

Doktorat
Master
Bash
Bachelor
Computertechnik
Scripting
Elektrotechnik
Python
Design Patterns

Vollständige Stellenbeschreibung

At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Senior Formal Verification (FV) Engineer to join one of our clients' teams.

Reporting directly to the Vector Unit Verification Lead, this is a highly technical Individual Contributor (IC) role. In this position, you will be the dedicated formal expert for the VU team, responsible for designing scalable formal testbenches, writing mathematical properties, and ensuring the absolute algorithmic and architectural integrity of our vector pipeline. You will work side-by-side with VU microarchitects to hunt down deep corner-case bugs and achieve formal sign-off on high-complexity arithmetic and execution blocks.

Key Responsibilities

Block-Level Execution & Convergence Engineering (90%)

End-to-End Testbench Ownership: Design, deploy, and maintain robust formal verification environments for complex Vector Unit sub-blocks (e.g., Vector Execution Pipelines, Vector Register File/Rename interfaces, and Vector Floating-Point Units).
Datapath & Arithmetic Verification: Implement advanced word-level modeling, bit-blasting, and algebraic rewriting strategies to verify complex IEEE-754 floating-point and integer vector arithmetic units.
Proof Convergence Management: Independently diagnose and resolve proof-convergence failures, over-constraints, and state-space explosions using advanced reduction techniques (e.g., case-splitting, black-boxing, and abstraction modeling).
RISC-V Vector Compliance: Develop formal environments to mathematically prove that the VU pipeline strictly complies with the RISC-V Vector (V) Extension specification.
Simulation Partnership: Collaborate closely with VU simulation engineers to define a razor-sharp boundary between simulation and formal verification, ensuring maximum bug-hunting efficiency and zero coverage gaps.

Embedded Mentorship & Best Practices (10%)

Formal-Friendly Design: Partner with VU microarchitects during early-stage RTL development to drive formal-friendly coding styles and structural design patterns.
SVA Propagation: Review and refine SystemVerilog Assertions (SVA) written by design and simulation peers, establishing best practices for block-level assertions within the VU team.

Education: B.S./M.S. in Computer Engineering, Electrical Engineering, or Computer Science with practical industry execution; or a Ph.D. with a research focus on formal methods or computer arithmetic.
Experience: 5+ years of production-grade hardware verification experience (or Ph.D. + 1–3 years) with a strong, proven track record of applying formal verification to CPU, GPU, or DSP execution pipelines.
Collaboration Style: A self-driven engineer who enjoys deep mathematical puzzles, collaborates seamlessly within a localized block-level team, and can translate complex proof counter-examples into actionable bugs for designers.
Datapath Validation Focus: Strong specialization in arithmetic formal verification, algebraic rewriting, and word-level modeling. Familiarity with control-path formal techniques (liveness, safety properties) is highly welcome.
Vector Microarchitecture: Good working knowledge of high-width execution pipelines, vector execution units, or floating-point/integer arithmetic hardware. Experience with Out-of-Order execution mechanics is a plus.
Formal Tools: Proficient command of commercial EDA formal tools (e.g., Cadence JasperGold/DPV, Synopsys VC Formal, Siemens OneSpin) and their specialized mathematical/datapath apps.
Languages: Native fluency in SystemVerilog and SystemVerilog Assertions (SVA). Scripting proficiency (Python, Tcl, or Bash) for testbench automation.

Nice to Have

RISC-V Core Verification.
RISC-V Ecosystem: Familiarity with the RISC-V Architecture, specifically the Vector (V) and Floating-Point (F/D) extension ecosystems.
Emulation platforms (Veloce, ZeBu).
Core/Bus interface protocols (e.g., AXI/CHI).

Direkt bewerben

Erweiterte Suche

platform engineer Jobs in stuttgart, bw

Senior Formal Verification Engineer

Staff Software Engineer - Linux Build Systems & Toolchain

Trainee Cloud & Data - Dein Einstieg in Artificial Intelligence & Data (m/w/d)

Senior Backend / Infrastructure Engineer (m/w/d) für das INSPO Team // Remote möglich

Staff Software Engineer - Fullstack

Senior/Staff Software Engineer Java

R&D Engineer (m/f/d) Software Development (Java)

Integration Engineer - Enterprise Integrations (f/m/x)

Data Scientist

BOC Specialist 4 - Stuttgart, Germany

Software Engineer C#/C++ - AWG with Focus on Hardware and Measurement Science

Product & Platform Engineering Expert (all genders)

EUCOM Cyber Operations Systems Engineer

Principal Security Engineer

PREEvision Engineer (m/w/d)

R&D Engineer, Hardware - High Speed Digital Board Design

Principal Data Engineer (m/f/d)

AI DevOps Engineer (all genders)

Work Student, Quality Assurance

Data Platform Architect (w/m/d)

Ich möchte aktuelle Job-E-Mails für Stellen als platform engineer in stuttgart, bw erhalten

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