20 beste Stellen als verification engineer (m/f/d) in perlach – aktuell auf Personalsuche

Experienced AMS Analog Layout Engineer (f/m/d)
Apple —München
- Bachelor
- Aufstiegsmöglichkeiten
Senior Digital IP Verification Engineer (f/m/d)
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Isar Aerospace SE —Ottobrunn
- Bachelor
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NXP Semiconductors —München
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Apple —München
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Dcubed —Germering
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AstraZeneca —München
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Experienced AMS Analog Layout Engineer (f/m/d)

Apple -
München

Jetzt bewerben

Details zur Stelle

Leistungen

Aufstiegsmöglichkeiten

Qualifikationen

Bachelor

Vollständige Stellenbeschreibung

As a member of Apple’s Analog Mixed-Signal layout team, you will be working on the newest technology nodes to build world-class custom analog macros, IO's, etc. This is a dynamic work environment with endless learning opportunities working in the AMS design team with members of integration, CAD, circuit and technology engineering.

At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and especially talented Analog Layout Designer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every day.

As a Senior Layout Engineer, you'll play a crucial role in translating design concepts into silicon, collaborating closely with circuit designers, and leveraging sophisticated tools. Your work will involve crafting custom analog designs to optimize the performance of Apple's world-class products. In this dynamic and innovative environment, you'll have endless learning opportunities while collaborating across dedicated multidisciplinary teams

Description
Senior Layout Engineers are pivotal in delivering Analog Mixed-Signal IP in a SOC flow. You will collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs. Your responsibilities include crafting sophisticated layouts for mixed-signal and analog circuits, reviewing floorplans, and analyzing intricate circuits with circuit designers. You'll run complete sets of design verification tools, plan/schedule work,
and coordinate vital layout tradeoffs. Interpretation of LVS, DRC, and ERC reports is key to finding the fastest way to complete the layout, exceeding engineering specifications and expectations.

This job is right for you if you are a self-motivated engineer passionate about working with groundbreaking technology. You want to accelerate career growth, thrive in a results- oriented environment, and contribute to the development of revolutionary Apple products. The roles include crafting upcoming products, challenging oneself, and broadening skillsets in a dynamic, innovative work culture

Preferred Qualifications
Bachelor’s degree in Electric Engineering or relevant experience
Excellent knowledge of Mixed-Signal and RF Integrated Circuits is helpful
Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.

Minimum Qualifications
Extensive years of experience in analog/mixed-signal layout design, with expertise in deep
submicron CMOS circuits and extensive years in FinFET technologies experience.
Proficiency in SKILL, Perl, TCL, Shell, and/or Python Programming/scripting.
Familiar with Machine Learning and AI concepts.
Track record in implementing analog layout designs, achieving optimal performance (eg.
Matching, low noise, and low power consumption.
Must recognise failure-prone circuit and layout structures, have experience with analog and DFM best practices, and be able to identify the best approach to solving problems.
High proficiency in custom and standard cell-based floor-planning and hierarchical layout assembly.
Technical understanding of IR drop, RC delay, electromigration, self-heating, and coupling
capacitance.
High proficiency in interpreting physical verification reports (DRC, ERC, LVS, etc.)
Experience using Cadence Virtuoso's advanced features (XL, EAD, APR, and Constraint Manager)
Excellent communication skills and ability to collaborate effectively with multi-functional teams.

Additional skill:
Cadence Innovus
CAD Automation experience
PCell creation experience
Proficiency in English language is required

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verification engineer (m/f/d) Jobs in perlach

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Ich möchte aktuelle Job-E-Mails für Stellen als verification engineer (m/f/d) in perlach erhalten

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