11 beste Stellen als electrical engineer in stuttgart – aktuell auf Personalsuche

Senior ASIC Design Engineer DfT (m/f/d)
Advantest —Böblingen
- Informatik
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Test Manager (m/f/d)
Advantest —Böblingen
- Informatik
- Wartung
- Master
Senior ASIC post-silicon validation engineer (m/f/d)
Advantest —Böblingen
- Informatik
- Datenanalyse
- Java
RF/mmWave IC & SiP Design Manager (m/f/d)
Keysight Technologies, Inc. —Böblingen
- Vollzeit
- Doktorat
- Master
- Bachelor
11 Tage
Senior RF / Analog Design Engineer (m/f/d)
Q.ANT GmbH —Stuttgart
- Vollzeit
- Doktorat
- Datenanalyse
- Englisch
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Global Product Manager (m/f/d) - Software & System Solutions
TE Connectivity —Waiblingen
- Master
- Bachelor
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Sales Manager Quantum Solutions
Quantum Machines —Stuttgart
- Vollzeit
- CRM-Software
- Vertrieb
- Salesforce
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Senior PIC Characterization Engineer - TFLN / High-Speed (f/m/d)
Q.ANT GmbH —Stuttgart
- Vollzeit
- Doktorat
- Datenanalyse
- Master
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Project Manager ASIC Design (m/f/d)
Advantest —Böblingen
- Englisch
- Elektrotechnik
- Kommunikationsfähigkeit
(Senior) PIC Design Engineer - Architecture & Fiber Coupling (f/m/d)
Q.ANT GmbH —Stuttgart
- Vollzeit
- Doktorat
- Englisch
- Master
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Senior Photonics Packaging Engineer RF (f/m/d)
Q.ANT GmbH —Stuttgart
- Vollzeit
- Doktorat
- CAD
- Englisch
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Senior ASIC Design Engineer DfT (m/f/d)

Advantest -
Böblingen

Jetzt bewerben

Details zur Stelle

Qualifikationen

Informatik
Verilog
Physik
Elektrotechnik

Vollständige Stellenbeschreibung

Join a global, highly skilled engineering team at the heart of Advantest's cutting edge IC test solutions. As a Digital ASIC Design Engineer, you will help create the key technologies that enable the next generation of semiconductor testing.
You will work on complex mixed signal ASICs used in Advantest's industry leading testers, taking digital modules and subsystems from first concept all the way to silicon in the final system, giving you true end to end ownership.
In this role, you will collaborate closely with system architects and design engineers. You will have a focus on generating test structures and memory BIST into existing circuity of IP blocks and the chip top level. You will use tools for pattern generation, keep power consumption under control, solve challenging technical problems, and deliver high quality results on schedule and at scale.

Job Duties & Responsibilities

Requirements gathering and elicitation for IP
Architecture development for CMOS IP designs
Design and RTL coding of digital and full-custom modules
Verification on module and chip level including test plan/cases generation.
Design for Test in existing IP and chip top level, implementation of memory BIST
Support for floor-planning and physical design
Test pattern generation
Collaboration with other functions

Requirements:

BS in Electrical Engineering/Physics/Computer Science or equivalent with over
5 years' experience in Design for Test and BIST
Knowledge of digital, mixed signal, RF and power device test methodologies
Experience in Register Transfer Level (RTL) coding (Verilog and System Verilog)
Experience with standard simulation tools for digital designs
Ability to work in a fast paced, project oriented, team environment.
Positive attitude and excellent communication skills are a must.

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Erweiterte Suche

electrical engineer Jobs in stuttgart

Senior ASIC Design Engineer DfT (m/f/d)

Test Manager (m/f/d)

Senior ASIC post-silicon validation engineer (m/f/d)

RF/mmWave IC & SiP Design Manager (m/f/d)

Senior RF / Analog Design Engineer (m/f/d)

Global Product Manager (m/f/d) - Software & System Solutions

Sales Manager Quantum Solutions

Senior PIC Characterization Engineer - TFLN / High-Speed (f/m/d)

Project Manager ASIC Design (m/f/d)

(Senior) PIC Design Engineer - Architecture & Fiber Coupling (f/m/d)

Senior Photonics Packaging Engineer RF (f/m/d)

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