Gehälter für die Stelle „Verification Engineer“ in Bayern

Create and define verification plans. Develop assertions in System Verilog for formal verification. Provide proactive support to internal stakeholders of our…

Support, maintain and further improve Infineon’s IC design methodology with focus on analog verification. More than 5 years of professional experience in the…

Verification Criteria: Establish unified verification criteria to harmonize hardware validation, firmware testing, and software QA processes.

Establish formal verification as a standard method in IP verification. The ability to excite and enable verification engineers to use formal methods.

Develop high-quality software tools for I/O library development and verification using modern programming and scripting languages.

Hands-on experiences in SoC verification. Familiarity with verification environments e.g. UVM, System Verilog is an advantage.