14 beste Stellen als validation expert in bayern – aktuell auf Personalsuche

Senior Formal Verification Engineer
TechBiz Global GmbH —Augsburg
- Vollzeit
- Homeoffice
- Doktorat
- Master
- Bachelor
Direkt bewerben
5 Tage
Sachbearbeiter - Rechnungswesen Rechnungsbearbeitung / SAP VIM (all genders) in Teilzeit
Zentrale der Fraunhofer-Gesellschaft —München
- Teilzeit
- Microsoft Word
- Microsoft Excel
- Textverarbeitung
- Weiterbildungsprogramme
Principal Analog Engineer - Intelligent Power Devices
Renesas Electronics —München
- Vollzeit
- Hybrides Arbeiten
- Führungserfahrung
Direkt bewerben
14 Tage
Solution Architect - Implementation Lead
Resaro AI —München
- Vollzeit
- Hybrides Arbeiten
- Künstliche Intelligenz
- Python
Direkt bewerben
4 Tage
Working Student Software Engineering Python (all genders)
Avelios Medical GmbH —München
- Teilzeit
- Informatik
- Java
- Master
- Flexible Arbeitszeiten
Embedded Systems Working Student
Cartken —München
- Teilzeit
- C++
Direkt bewerben
Senior Embedded Software Developer (C) (f/m/d)
Munich Electrification —München
- Vollzeit
- Hybrides Arbeiten
- C++
- Homeoffice-Möglichkeit
Direkt bewerben
GES Process Lead (f/m/d) (MUSE) - Associate Director
MSD —Unterschleißheim
- Vollzeit
- Bachelor
- Ohne Reiseanteil
- Führungserfahrung
14 Std.
Senior Hardware Design Engineer (f/m/d)
Munich Electrification —München
- Vollzeit
- Hybrides Arbeiten
- Homeoffice-Möglichkeit
Direkt bewerben
Functional Safety Architect (f/m/d)
Renesas Electronics —Germering
- Vollzeit
- Master
- Bachelor
- Künstliche Intelligenz
Direkt bewerben
7 Tage
Working Student Software Engineering Python (all genders)
Avelios Medical —München
- Teilzeit
- Informatik
- Java
- Master
- Flexible Arbeitszeiten
Product Owner - VDC Manager (f/m/d)
Thinkproject Holding GmbH —München
- Vollzeit
- Azure
- DevOps
- Windows
3 Std.
Principal Technical Leader for Automotive Systems Power
Renesas Electronics —München
- Vollzeit
- Hybrides Arbeiten
- Bachelor
- Elektrotechnik
- Künstliche Intelligenz
Direkt bewerben
5 Tage
Werkstudent*in (w/m/d) Clinical Insights for AI in Medical Imaging
Siemens Healthineers —Forchheim
- Teilzeit
- Hybrides Arbeiten
- Datenanalyse
- Künstliche Intelligenz
- Python
1 Tag

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Sachbearbeiter - Rechnungswesen Rechnungsbearbeitung / SAP VIM (all genders) in Teilzeit
Zentrale der Fraunhofer-Gesellschaft —München
Zudem betreut die Abteilung das SAP-Modul VIM (Vendor Invoice Management, inklusive Validation), das zentrale Rechnungseingangsportal für alle Fraunhofer-…

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Senior Formal Verification Engineer

TechBiz Global GmbH
Augsburg

Direkt bewerben

Details zur Stelle

Vollzeit
vor 5 Tagen

Qualifikationen

Doktorat
Master
Bash
Bachelor
Computertechnik
Scripting
Elektrotechnik
Python
Design Patterns

Vollständige Stellenbeschreibung

At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Senior Formal Verification (FV) Engineer to join one of our clients' teams.

Reporting directly to the Vector Unit Verification Lead, this is a highly technical Individual Contributor (IC) role. In this position, you will be the dedicated formal expert for the VU team, responsible for designing scalable formal testbenches, writing mathematical properties, and ensuring the absolute algorithmic and architectural integrity of our vector pipeline. You will work side-by-side with VU microarchitects to hunt down deep corner-case bugs and achieve formal sign-off on high-complexity arithmetic and execution blocks.

Key Responsibilities

Block-Level Execution & Convergence Engineering (90%)

End-to-End Testbench Ownership: Design, deploy, and maintain robust formal verification environments for complex Vector Unit sub-blocks (e.g., Vector Execution Pipelines, Vector Register File/Rename interfaces, and Vector Floating-Point Units).
Datapath & Arithmetic Verification: Implement advanced word-level modeling, bit-blasting, and algebraic rewriting strategies to verify complex IEEE-754 floating-point and integer vector arithmetic units.
Proof Convergence Management: Independently diagnose and resolve proof-convergence failures, over-constraints, and state-space explosions using advanced reduction techniques (e.g., case-splitting, black-boxing, and abstraction modeling).
RISC-V Vector Compliance: Develop formal environments to mathematically prove that the VU pipeline strictly complies with the RISC-V Vector (V) Extension specification.
Simulation Partnership: Collaborate closely with VU simulation engineers to define a razor-sharp boundary between simulation and formal verification, ensuring maximum bug-hunting efficiency and zero coverage gaps.

Embedded Mentorship & Best Practices (10%)

Formal-Friendly Design: Partner with VU microarchitects during early-stage RTL development to drive formal-friendly coding styles and structural design patterns.
SVA Propagation: Review and refine SystemVerilog Assertions (SVA) written by design and simulation peers, establishing best practices for block-level assertions within the VU team.

Education: B.S./M.S. in Computer Engineering, Electrical Engineering, or Computer Science with practical industry execution; or a Ph.D. with a research focus on formal methods or computer arithmetic.
Experience: 5+ years of production-grade hardware verification experience (or Ph.D. + 1–3 years) with a strong, proven track record of applying formal verification to CPU, GPU, or DSP execution pipelines.
Collaboration Style: A self-driven engineer who enjoys deep mathematical puzzles, collaborates seamlessly within a localized block-level team, and can translate complex proof counter-examples into actionable bugs for designers.
Datapath Validation Focus: Strong specialization in arithmetic formal verification, algebraic rewriting, and word-level modeling. Familiarity with control-path formal techniques (liveness, safety properties) is highly welcome.
Vector Microarchitecture: Good working knowledge of high-width execution pipelines, vector execution units, or floating-point/integer arithmetic hardware. Experience with Out-of-Order execution mechanics is a plus.
Formal Tools: Proficient command of commercial EDA formal tools (e.g., Cadence JasperGold/DPV, Synopsys VC Formal, Siemens OneSpin) and their specialized mathematical/datapath apps.
Languages: Native fluency in SystemVerilog and SystemVerilog Assertions (SVA). Scripting proficiency (Python, Tcl, or Bash) for testbench automation.

Nice to Have

RISC-V Core Verification.
RISC-V Ecosystem: Familiarity with the RISC-V Architecture, specifically the Vector (V) and Floating-Point (F/D) extension ecosystems.
Emulation platforms (Veloce, ZeBu).
Core/Bus interface protocols (e.g., AXI/CHI).

Direkt bewerben

Erweiterte Suche

validation expert Jobs in bayern

Senior Formal Verification Engineer

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GES Process Lead (f/m/d) (MUSE) - Associate Director

Senior Hardware Design Engineer (f/m/d)

Functional Safety Architect (f/m/d)

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Product Owner - VDC Manager (f/m/d)

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