20 beste Stellen als analog design engineer in perlach – aktuell auf Personalsuche

Sr. Engineer, Digital Design
SiTime Corporation —München
- Vollzeit
- Doktorat
- Master
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Direkt bewerben
Electronics Design Engineer
Terra Quantum —München
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Identiv —Sauerlach
- 75.000 € – 100.000 € pro Jahr
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- Master
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Senior Staff Engineer Automation & Digitalization for IP Development (f/m/div)
Infineon Technologies AG —München
- Informatik
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Senior Digital Design Engineer (m/w/d)
TDK-Micronas GmbH —München
- 95.000 € – 110.000 € pro Jahr
- Vollzeit
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- Flexible Arbeitszeiten
12 Tage
RF/Analog IC Layout Engineer (m/f/d)
Apple —München
- Master
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10 Tage
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Quantum-Systems GmbH —Gilching
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Analog Mixed‑Signal Layout Engineer (all gender)
ALTEN —München
- Vollzeit
- Elektrotechnik
- Flexible Arbeitszeiten
Direkt bewerben
7 Tage
Experienced AMS Analog Layout Engineer (f/m/d)
Apple —München
- Bachelor
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Principal Engineer, Analog Mixed-Signal Desig
SiTime Corporation —München
- Vollzeit
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System Integration Engineer (m/f/d)
Quantum-Systems GmbH —Gilching
- Vollzeit
- Bachelor
- Flexible Arbeitszeiten
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Senior Staff Engineer Analog Verification Methodology (f/m/div)
Infineon Technologies AG —München
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Principal Engineer Design
Infineon Technologies AG —München
9 Tage
Quantum Integration Engineer
planqc —Garching bei München
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Firmware Engineer (f/m/d) for Embedded / Automotive / ASIP RISC‑-V
Renesas Electronics —Germering
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AMS Lab Validation Engineer (m/f/d)
Apple —München
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Principal Analog Engineer - Intelligent Power Devices
Renesas Electronics —München
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AMS STA / Timing Engineer (m/f/d).
Apple —München
- Master
- Bachelor
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- Aufstiegsmöglichkeiten
Experienced Field Application Engineer
GLOBALFOUNDRIES —München
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Staff Engineer, Field Applications
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- Mit Reiseanteil

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analog design engineer jobs near perlach

Sr. Engineer, Digital Design

SiTime Corporation -
München

Direkt bewerben

Details zur Stelle

Vollzeit

Qualifikationen

Doktorat
Signalverarbeitung
Master
Computertechnik
Elektrotechnik

Vollständige Stellenbeschreibung

About SiTime

SiTime Corporation is a precision timing company. Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 3 billion devices shipped, SiTime is changing the timing industry. For more information, visit www.sitime.com.

Job Summary

We at SiTime take pride in being the only company in the market that offers MEMS-based timing solutions. Our MEMS dies are uniquely complemented by our CMOS dies in the same package. We use state-of-the-art analog and digital circuits to achieve very aggressive design specs for our timing solutions. Our precision timing products keep pushing the boundaries of the industry across all dimensions and are by far superior to our competition. This has enabled us to continuously gain market share.

This has been achieved by pushing the innovation boundaries in MEMS and CMOS. Consisting of analog and digital blocks, our CMOS dies present unique technical challenges. The digital portion of our chips has been growing in the past few years and is expected to grow more rapidly in the upcoming years as our functionality and features scale up. To address our unique technical challenges, we are looking for a strong Senior Logic Design Engineer with a solid background in key digital design and implementation areas.

It is not necessary to meet all job requirements to be a qualified candidate for the position.

Responsibilities:

Developing micro-architecture specification of the logic circuit from reading and comprehending the Product Requirement Document (PRD).
Developing the Register Transfer Level (RTL) design from the micro-architecture specification using Verilog or SystemVerilog as the HDL.
Developing standalone test benches to verify the RTL behavior.
Writing and verifying SystemVerilog Assertions (SVA) for a design.
Writing timing constraints and clock definition for synthesis and place and route tools.
Running industry-standard synthesis tools (e.g., Genus or Design Compiler) and being able to fix timing problems if they arise.
Understanding various design tradeoffs including timing/area/power and knowing how to improve them.
Reading and understanding the Static Timing Analysis (STA) reports from an industry-standard STA tool (e.g., Prime Time).
Cross-functional interactions and communication with various teams within SiTime including analog, verification, backend, system, and test engineering teams.
Post-Si bring-up, validation, and debugging.

Qualifications & Requirements:

Master’s degree in electrical engineering plus 5 years of relevant work experience in the industry.
Excellent verbal and written communication skills in English.
Proficient in Verilog and SystemVerilog.
Expertise in digital logic design fundamentals such as clock divider circuits, multi-clock logic designs, CDC, FIFO, FSM, etc.
Experience in designing mixed-signal digital logic.
Basic understanding of Discrete time Signal Processing theory, FIR, and IIR filter design.
Solid experience in digital design flow including RTL design, synthesis, timing constraints, and STA.
Skilled in scripting languages Perl/Tcl/Python.

Desired Characteristics & Attributes:

Ph.D. in electrical/computer engineering plus 3 years of relevant industry experience.
2-5 years of experience in designing high-precision digital arithmetic logic and Digital Signal Processing.
2-5 years of experience in designing Digital Phase-Locked Loops (DPLL).
Experience in complex FSM design.
Familiarity with MATLAB, Simulink, or any other high-level modeling tools.
Experience in low-power digital design flow.
Basic understanding of the Control Theory.

The actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.

SiTime compensation packages includes base salary, bonus based on achieving your innovation goals and equity.

Learn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique.

Innovation on Top – Philosophies of Innovation with Rajesh Vashist
Fabrication Knowledge – An Interview with Rajesh Vashist
SiTime Corporation – YouTube

#LI-SITIME

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Erweiterte Suche

analog design engineer Jobs in perlach

Sr. Engineer, Digital Design

Electronics Design Engineer

Analog Hardware Engineer

Senior Staff Engineer Automation & Digitalization for IP Development (f/m/div)

Senior Digital Design Engineer (m/w/d)

RF/Analog IC Layout Engineer (m/f/d)

Prototyping Engineer (m/f/d) – Test Benches & Validation

Analog Mixed‑Signal Layout Engineer (all gender)

Experienced AMS Analog Layout Engineer (f/m/d)

Principal Engineer, Analog Mixed-Signal Desig

System Integration Engineer (m/f/d)

Senior Staff Engineer Analog Verification Methodology (f/m/div)

Principal Engineer Design

Quantum Integration Engineer

Firmware Engineer (f/m/d) for Embedded / Automotive / ASIP RISC‑-V

AMS Lab Validation Engineer (m/f/d)

Principal Analog Engineer - Intelligent Power Devices

AMS STA / Timing Engineer (m/f/d).

Experienced Field Application Engineer

Staff Engineer, Field Applications

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