20 beste Stellen als high performance computing in münchen – aktuell auf Personalsuche

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Software Engineer II (C++)

Cadence Design Systems -
München

Jetzt bewerben

Details zur Stelle

Vollzeit
vor 3 Stunden

Qualifikationen

Informatik
UNIX
Master
Verilog
C++
Bachelor
Scripting
Softwareentwicklung
Linux
Elektrotechnik

Vollständige Stellenbeschreibung

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title: Software Engineer II

Location: Munich, Germany or Cambridge, UK

Reports to: Sr Software Engineering Group Director

Job Overview:

As a Software Engineer II on the Innovus and Genus database team within Cadence’s Digital Design Implementation (DDI) business unit, you will design and build the database infrastructure that underpins some of the world’s most advanced chip-design tools. Your work will directly shape the performance, scalability, and reliability of EDA software used by leading semiconductor companies globally - enabling them to bring next-generation integrated circuits to market faster and with greater confidence.

This is an opportunity to work on technically challenging, high-impact problems at the heart of modern electronic design.

Job Responsibilities:

Design, develop, and optimise EDA database infrastructure software, including data-model enhancements, API definitions, and class implementations.
Investigate and resolve customer-reported defects, delivering robust fixes and clear root-cause analysis within agreed timelines.
Collaborate with application engineering teams to profile, benchmark, and improve database API performance and code quality.
Reduce database memory footprint to support very large-scale IC designs, enabling customers to tackle increasingly complex chips.
Contribute to architectural discussions and technical design reviews, proposing solutions that balance performance, maintainability, and long-term scalability.
Write clean, well-tested code and accompanying documentation that meets Cadence’s engineering standards.
Participate actively in agile ceremonies - sprint planning, stand-ups, and retrospectives - as a constructive team contributor.
Stay current with relevant developments in EDA, database architecture, and AI-assisted development tooling, and share insights with the broader team.

Job Qualifications:

Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field - or equivalent professional experience.
Min 2 years of professional software development experience in a relevant engineering environment.
Strong proficiency in C++, including familiarity with modern C++ standards and best practices.
Understanding of IC design data models, database architecture, and efficient data-access algorithms.
Experience working in UNIX and/or Linux development environments.
Excellent software engineering fundamentals: clean code practices, debugging, testing, and performance analysis.

Additional Skills/Preferences:

Experience with Tcl scripting in an EDA or automation context.
Familiarity with Verilog Hardware Description Language.
Knowledge of the IEEE 1801 Power Format (UPF) standard.
Practical experience using AI-assisted coding tools (e.g., GitHub Copilot, Claude Code, or similar) to accelerate and improve development workflows.

Additional Information:

You will join a globally distributed team with colleagues across Europe, the United States, and Asia, collaborating across time zones in an inclusive, high-trust environment. The role supports hybrid working at either our Munich or Cambridge offices. Core tools include C++, Tcl, Linux, and internal EDA toolchains. You will work closely with application engineering teams and, where relevant, engage with customer-facing technical colleagues.

Check what we can offer you:

Competitive salary
30 days holiday per year
Group Pension Plan
JobRad
EGYM Wellpass
Lunch vouchers
5 days paid time to volunteer to give back to our communities
Employee Stock Purchase Plan

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

We’re doing work that matters. Help us solve what others can’t.

Jetzt bewerben

Erweiterte Suche

high performance computing Jobs in münchen

Software Engineer II (C++)

Working Student Machine Learning (all genders)

Head of IT Platform & Services

Solution Architect for Finance Group Systems (m/f/d)*

Computer Vision & AI Engineer - Interceptor C‑UAS (m/f/d)

Electronics Design Engineer

Senior Manager, Software Engineering - JAX

Senior Solution Manager EDGE & AI

Intern Machine Learning (all genders)

Solution Architect - Agile Teams

Mid/Senior Solution Architect - Germany

Senior Machine Learning Engineer (m/f/d)

IT Enterprise Architect (m/w/d)

(Lead) IoT Solutions Engineer (m/f/d)

Technical Team Lead - Robotics & Autonomous Systems (m/f/d)

Business Operations Sales Analyst

Principal AI Vehicle Architect (f/m/x)

Intern Applications Engineering (f/m/d)

Quantum Software Engineer, Benchmarking and Error Reduction

HPC Systems Administrator

Ich möchte aktuelle Job-E-Mails für Stellen als high performance computing in münchen erhalten

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We’re doing work that matters. Help us solve what others can’t.

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