Gehälter für die Stelle „Design Verification Engineer“ in Sachsen

Create verification plans and develop verification environments based on Unified Verification Methodology (UVM). Self-driven and hands-on way of working.

Asic design and mixed signal verification knowledge preferably in memory design. Run regression tests reporting results to design engineer.

Basic knowledge of the RTL2GDS design flow. Racyics® is Europe’s leading design service provider for mixed-signal system-on-chip design and turnkey services in…

Support, maintain and further improve Infineon’s IC design methodology with focus on analog verification. More than 5 years of professional experience in the…

Hands-on experience in circuit design, layout implementation and verification with Cadence Virtuoso. Develop behavioral circuit models for verification.

Perform top-level simulations to validate and optimize design concepts. Present your results in design reviews and demonstrate compliance with specifications.

85.000 € – 105.000 € pro Jahr

vor 11 Tagen