Gehälter für die Stelle „Verification Engineer“ in Nordrhein-Westfalen

Experience with formal and dynamic verification. Experience in block level and sub-system or top level verification. Proficiency in SystemVerilog and UVM.

Knowledge of semiconductor, ASIC, FPGA, or hardware verification workflows. Set up a Continuous Integration flow.

Build verification infrastructure for the block. Proficiency in developing verification environments from scratch.

vor 2 Tagen

Thus, KBR GmbH’s employees contribute to a wide range of projects including astronaut selection and training, ongoing medical operations to the International…

vor 14 Tagen

Simulation Partnership: Collaborate closely with VU simulation engineers to define a razor-sharp boundary between simulation and formal verification, ensuring…

vor 2 Tagen

You are part of a cross-functional agile team and cooperate with product owner, software developers, other verification and DevOps engineers on a daily basis.