Gehälter für die Stelle „Design Verification Engineer“ in Deutschland

Experience with formal and dynamic verification. Experience in block level and sub-system or top level verification. Proficiency in SystemVerilog and UVM.

Knowledge of semiconductor, ASIC, FPGA, or hardware verification workflows. Set up a Continuous Integration flow.

Perform system- and transistor-level design, simulation, and verification. Experience mentoring junior engineers or leading small technical efforts.

BMS/EMS Design as part of a multi discipline projects team throughout all project phases. Generate detailed scope of work packages for BMS contractor for tender…

vor 22 Stunden

Excellent problem-solving and analytical skills, with the ability to troubleshoot and resolve complex physical design issues. Knowledge of the JIRA tool.

Experience with environmental auditing and compliance verification. The environmental engineer will work with internal and external partners that include…