Gehälter für die Stelle „Verification Engineer“ in Nordrhein-Westfalen

Experience with formal and dynamic verification. Experience in block level and sub-system or top level verification. Proficiency in SystemVerilog and UVM.

Knowledge of semiconductor, ASIC, FPGA, or hardware verification workflows. Set up a Continuous Integration flow.

Build verification infrastructure for the block. Proficiency in developing verification environments from scratch.

vor 3 Tagen

Simulation Partnership: Collaborate closely with VU simulation engineers to define a razor-sharp boundary between simulation and formal verification, ensuring…

vor 3 Tagen

Experience in cross-functional collaboration with design, verification, product engineering, and test engineering teams.

Experience with Linux (and its drivers) and PCIe devices. Solid knowledge and experience in dynamic thermal management (DTM). Knowledge of the JIRA tool.