Gehälter für die Stelle „Design Verification Engineer“ in Dresden, SN

Create verification plans and develop verification environments based on Unified Verification Methodology (UVM). Self-driven and hands-on way of working.

Asic design and mixed signal verification knowledge preferably in memory design. Run regression tests reporting results to design engineer.

Support, maintain and further improve Infineon’s IC design methodology with focus on analog verification. More than 5 years of professional experience in the…

Hands-on experience in circuit design, layout implementation and verification with Cadence Virtuoso. Develop behavioral circuit models for verification.

Basic knowledge of the RTL2GDS design flow. Racyics® is Europe’s leading design service provider for mixed-signal system-on-chip design and turnkey services in…

Execute existing and develop new trainings for the design and verification community at Infineon. Act as bridge between internal design and verification…