Gehälter für die Stelle „Verification Engineer“ in Nordrhein-Westfalen

Experience with formal and dynamic verification. Experience in block level and sub-system or top level verification. Proficiency in SystemVerilog and UVM.

Knowledge of semiconductor, ASIC, FPGA, or hardware verification workflows. Set up a Continuous Integration flow.

Build verification infrastructure for the block. Proficiency in developing verification environments from scratch.

vor 2 Tagen

Simulation Partnership: Collaborate closely with VU simulation engineers to define a razor-sharp boundary between simulation and formal verification, ensuring…

vor 2 Tagen

Using VisMockUp, Teamcenter, CATIA, FEDE-BOM and WERS professionally. Global teamwork with Product Development, Styling, Manufacturing, Purchase, Finance,…

vor 13 Tagen

Experience in cross-functional collaboration with design, verification, product engineering, and test engineering teams.